4094 8-bit 3-state serial-in/parallel-out shift register with output latches. Y is Q0 delayed by half a cycle (i.e. clocked on falling edge). +----------+ LE |1 +--+ 16| VCC D |2 15| OE CLK |3 14| P3 P7 |4 13| P2 P6 |5 4094 12| P1 P5 |6 11| P0 P4 |7 10| Y GND |8 9| Q0 +----------+